The present invention relates to a semiconductor memory device; and, more particularly, to a delay locked loop for use in a semiconductor memory device in order to compensate a clock skew.
A semiconductor memory device serves to store a data in a system which includes plural semiconductor devices. When a data processing device, e.g., a central processing unit (CPU), requires a data, the semiconductor memory device outputs a data corresponding to an address inputted by the data requiring device or stores a data received from the data requiring device into a memory cell corresponding to the address.
As an operational speed of the system is increased and a semiconductor integrating technology is developed, the semiconductor memory device is required to perform a data access operation at higher speed. For performing the data access operation at high speed, a synchronous memory device has been developed for performing the data access operation in synchronization with a system clock.
For improving the operational speed of the synchronous memory device, a double data rate (DDR) synchronous memory device has been developed for performing the data access operation in synchronization with both of a rising edge and a falling edge of the system clock.
Since the DDR synchronous memory device should input or output a data in synchronization with both of a rising edge and a falling edge of the system clock, the DDR synchronous memory device should process two data within one period of the system clock. That is, the DDR synchronous memory device should output a data or store a data at a rising edge and a falling edge of the system clock.
Particularly, the timing of outputting a data from the DDR synchronous memory device should be exactly synchronized with a rising edge or a falling edge of the system clock. For this, a data output circuit of the DDR synchronous memory device outputs a data in synchronization with a rising edge and a falling edge of the system clock.
However, the system clock inputted to a semiconductor memory device is inevitably delayed while the system clock passes through internal units of the semiconductor memory device, e.g., a clock input buffer and a transfer line for transferring a clock signal. Therefore, if the data output circuit outputs a data in synchronization with the delayed system clock, an external device receives a data which is not synchronized with a rising edge and a falling edge of the system clock.
For solving the above-mentioned problem, a semiconductor memory device includes a delay locked loop. The delay locked loop serves to compensate a delay amount generated while the system clock is transferred to the data output clock after the system clock is inputted to the semiconductor memory device.
The delay locked loop detects a delay amount generated while the system clock is transferred through the clock input buffer and the clock signal transfer line and delays the system clock corresponding to the detected delay amount to output the delayed system clock to the data output circuit. That is, by the delay locked loop, the system clock inputted to the semiconductor memory device is transferred to the data output circuit being delay-locked.
The data output circuit outputs a data in synchronization with the delay locked clock and, thus, an external device recognizes that the data is outputted in synchronization with the system clock. In an actual operation, the delay locked clock outputted from the delay locked loop is transferred to an output buffer one cycle prior to a point of time when a data should be outputted, and a data is outputted in synch with the transferred delay locked clock. Therefore, a data is outputted faster than a delay amount of the system clock generated by internal circuits of the semiconductor memory device while the system clock is transferred through the semiconductor memory device.
In this manner, a data can be outputted from a semiconductor memory device in synchronization with a rising edge and a falling edge of a system clock inputted to the semiconductor memory device. As a result, a delay locked loop serves to detect how faster a data should be outputted in order to compensate a delay amount of the system clock.
FIG. 1 is a block diagram depicting a conventional delay locked loop (DLL).
As shown, the delay locked loop includes a DLL control unit 10, a clock buffer unit 20, a clock buffer control unit 30, a first delay control unit 40A, a second delay control unit 40B, a mode generation unit 50, a phase comparison unit 60, a delay replica unit 70, a duty cycle correction (DCC) control unit 80 and an output driver 90.
The clock buffer unit 20 receives external clocks clk and clkb in order to generate a first internal clock signal clkin1, a second internal clock signal clkin2, a reference clock signal refclk and a clock control signal contclk. The buffer control unit 30 serves to control an operation of the clock buffer unit 20 according to an operation mode of the semiconductor memory device and receives control signals clkeb_com, rasidle and sapd to generate a clock buffer enable signal clkbuf_enb.
The phase comparison unit 60 compares an input clock and an output clock of the conventional delay locked loop in order to detect a phase difference between the input and the output clocks. That is, the phase comparison unit 60 compares a phase of the reference clock signal refclk and phases of feedback clock signals fbclkr and fbclkf in order to output the comparison result to the mode generation unit 50. Herein, the comparison result can be classified into three cases, i.e., a case requiring a fast mode (FM_pdout_r, FM_pdout_f), a case of a delay difference (co_r, co_f) and a case of a fine delay difference (fi_r, fi_f).
The mode generation unit 50 determines whether the conventional delay locked loop is in a locked state or the fast mode should be performed because of a large phase difference based on the comparison result in order to control the first and the second delay control units 40A and 40B.
Each delay amount of the first and the second delay control units 40A and 40B is determined by an output of the mode generation unit 50 in order to respectively delay the first and the second internal clock signals clkin1 and clkin2. The first and the second internal clock signals clkin1 and clkin2 are outputted as a rising delayed signal mixout_r and a falling delayed signal mixout_f after being delayed by the first and the second delay control units 40A and 40B respectively.
The DCC control unit 80 mixes the rising and the falling delayed signals mixout_r and mixout_f in order to generate a duty-corrected clock which has a 50% duty.
The output driver 90 receives an output of the DCC control unit 80 to generate DLL output signals irclkdll and ifclkdll.
The delay replica unit 70 models a delay amount added to the external clock before the external clock is transferred to a phase delay unit and a delay amount added to an output clock of the phase delay unit until the output clock is transferred to the outside. The delay replica unit 70 receives output signals ifbclkr and ifbclkf of the DCC unit 80 in order to delay the output signals ifbclkr and ifbclkf for the modeled delay amount, and outputs the delayed signals as the feedback clock signals fbclkr and fbclkf.
In order to reduce a power consumption or more correctly keep the delay locked state according to the operation mode of the semiconductor memory device, the DLL control unit 10 is included to control an operation of the conventional delay locked loop.
The DLL control unit 10 receives a DLL reset signal dll_resetb and a DLL disable signal dis_dll to generate a reset signal rst for controlling operations of internal blocks. The reset signal rst is inputted to the mode generation unit 50 and the DCC control unit 80.
FIG. 2 is a schematic circuit diagram showing the DLL control unit shown in FIG. 1.
As shown, the DLL control unit includes a plurality of inverters and a NAND gate for generating the reset signal rst by performing a logic operation to the DLL disable signal dis_dll for disabling the conventional delay locked loop and the DLL reset signal dll_resetb for resetting the conventional delay locked loop.
FIG. 3 is a schematic circuit diagram illustrating the output driver 90 shown in FIG. 1.
As shown, the output driver 90 includes a plurality of inverters. The output driver 90 receives the duty-corrected signals ifbclkr and ifbclkf whose duty ratio is 50:50 from the DCC control unit 80. By using one of the duty-corrected signals, i.e., ifbclkr, the output driver 90 generates a rising DLL output signal irclkdll and a falling DLL output signal ifclkdll. Herein, the unused duty-corrected signal, i.e, ifbclkf, is floated.
FIG. 4 is a schematic circuit diagram showing a first mode generator 52 included in the mode generation unit 50 shown in FIG. 1.
The first mode generator 52 shown in FIG. 4 serves to control the first delay control unit 40A. Although not shown, the mode generation unit 50 also includes a second mode generator for controlling the second delay control unit 40B.
The first mode generator 52 includes a fast mode detection unit 54 and a locked state detection unit 56 each of which includes a plurality of inverters and a flip-flop. According to the comparison result signals, i.e., FM_pdout, co_r and fi_r, of the phase comparison unit 60 and the reset signal rst outputted from the DLL control unit 10, the first mode generator 52 determines whether to operate the first delay control unit 40A at the fast mode or to inform the first delay control unit 40A of the locked state so that the delay control unit 40A no further performs the delay adjusting operation. Since an operation of the schematic circuit shown in FIG. 4 is well known to those skilled in the art, a detailed description of the operation is omitted.
FIG. 5 is a schematic circuit diagram depicting the DCC control unit 80 shown in FIG. 1.
As shown, the DCC control unit 80 includes a first mixer 82 and a second mixer 84 each of which includes a plurality of inverters controlled by a mixing activation signal.
The first mixer 82 mixes the rising delayed signal mixout_r outputted from the first delay control unit 40A with the falling delayed signal mixout_f outputted from the second delay control unit 40B in order to generate the rising duty-corrected signal ifbclkr by passing the rising delayed signal mixout_r and the falling delayed signal mixout_f respectively through a first group of inverters and a second group of inverters so that the rising duty-corrected signal ifbclkr has a 50% duty. Herein, the first group of inverters is controlled by the mixing activation signal en<0:n> and the second group of inverters is controlled by an inverted mixing activation signal enb<n:0>. The number of inverters included in the first group is same to that of the second group.
Meanwhile, the second mixer 84 receives the rising delayed signal mixout_r and the falling delayed signal mixout_f in order to correct a duty ratio of one of the received signals by passing the one of the received signals through a plurality of inverters and, then, outputs the duty-corrected signal as the falling duty-corrected signal ifbclkf.
Although not shown, the mixing activation signal en<0:n> and the inverted mixing activation signal enb<n:0> are generated by the reset signal rst outputted from the DLL control unit 10. Further, the DCC control unit 80 determines whether the duty ratio correction operation is normally performed in order to generate a DCC enable signal DCC_ENb.
The above-mentioned conventional delay locked loop includes two delay lines. When the delay locked state is broken due to external variations, e.g., an unstable power supply voltage and a distorted input clock, after the delay locking operation is completed, the delay locking operation should be performed again.
In this case, if the delay amount cannot be increased further, because all of the delay elements included in one of the delay lines are currently used for delaying an input signal, or if the delay amount cannot be decreased further, because none of the delay elements is currently used for delaying the input signal, the delay lines fail to readjust the delay amount. Accordingly, it is difficult for the DCC control unit 80 to generate a correct signal.